|
|
|
0-In's Archer Verification System Targets Verification Hot Spots
Easy-to-Use Archer Provides Complete Verification Solution
for Design Teams Working on Multi-Million Gate
ASIC and SoC Designs
SAN JOSE, Calif.—(BUSINESS WIRE)—Jan. 26, 2004—
Today 0-In Design Automation, the Assertion-Based Verification
Company, announced availability of the Archer Verification(TM) system,
a complete verification solution that is equal parts tools and
engineered methodology for the most critical verification issues
facing design teams developing multi-million gate ASIC and
system-on-chip (SoC) devices. Archer Verification adds automation to
methodologies, providing an efficient, robust and effective set of
solutions usable by all design engineers, not just verification
specialists. Archer Verification delivers the RTL-centric methods of
the verification process automation (VPA) initiative announced with
partners Verisity Ltd. and Novas Software Inc. (see
http://www.0-in.com/news/PR_031103_Strategic_collaboration.html).
"Providing verification solutions, rather than simply tools, has
allowed us to deploy formal verification technologies successfully in
many customer projects," said Steve White, 0-In's president and CEO.
"We realized early on that creating a usable, repeatable and effective
methodology for using formal technologies is as much engineering work
as creating the tools themselves. We have focused on combining first
class methods with superior technology to put enormous verification
power in the hands of engineers doing the front-line verification work
on leading-edge SoC designs."
"Throwing only tools or languages at the functional verification
problem just won't cut it anymore," said Steve Glaser, vice president
of corporate marketing and business development for Verisity. "By
automating well-defined processes across block, chip, system and
project levels, we can truly achieve a 10x boost in productivity --
this is what VPA is all about. With the Archer Verification System,
0-In is clearly helping our joint customers complete their VPA
solutions."
"The combination of strong tools and an efficient methodology is
at the heart of the VPA collaboration between Novas and 0-In," said
Dave Kelf, vice-president of marketing for Novas Software. "With the
release of the Archer Verification solution, 0-In has truly provided
winning assertion-based technology, further delivering on the VPA
concept."
Faster, Better, Measured Verification
The Archer Verification system brings verification closure to
users through:
-- More efficient verification: finds bugs faster in simulation
with assertions and enables more efficient debug of errors by
quickly identifying the root cause of bugs.
-- More complete verification: finds bugs missed by simulation
methods alone and automatically exercises corner cases and
coverage points.
-- Measurable verification closure: uses unified structural
coverage to provide measures of verification centered on
implementation.
"With nearly 20,000 licenses for 0-In products in use, we have a
broad range of customer experience on which to draw as we evolve and
enhance our product line," said 0-In co-founder and chief architect
Richard Ho. "The Archer Verification system leverages that experience
to provide comprehensive, packaged solutions that include appropriate
tools, verification IP, documentation and co-developed methodologies
for specific areas of verification. As customers have told us what
works best in the field, we have responded with products that make
these methods available to the entire customer base."
Platform Independent, Standards-based Technologies
The Archer Verification system provides horizontal solutions for
functional verification based on comprehensive, easy-to-use and
powerful verification IP; a technologically superior toolset and
methodologies honed on customer designs. The Archer solutions support
all the major verification platforms from EDA vendors including those
from Cadence, Verisity, Synopsys and Mentor Graphics. It also supports
all emerging assertion standards from Accellera and IEEE. By providing
platform independent, standards-based advanced functional verification
capabilities, Archer gives users the flexibility to choose a
simulation infrastructure without sacrificing verification power.
Complete and Robust Verification Methodologies
Archer Verification is the next evolutionary step for
assertion-based and formal verification. The Archer solutions target
block, sub-system and chip level functional verification. These
solutions enable a complete verification methodology that addresses
both specification- and register-transfer level (RTL) functionality
and corner-cases. In particular, Archer provides methods and tools to
execute items of the user's verification plan that cannot be addressed
in any other way:
-- Verification hot spots: critical logic that is difficult to
verify in simulation.
-- Critical coverage points: implementation corner-cases that
must be exercised and covered.
With Archer Verification, customers are provided with
methodologies to verify critical items in their own verification plan.
Each methodology applies the most efficient, most complete method and
set of tools for each particular verification issue. Coverage metrics
are provided to measure progress towards closure.
To execute the methodologies efficiently, Archer Verification
provides a set of key technologies and capabilities:
-- Verification IP - including CheckerWare(R), the industry's
most comprehensive library of assertion checkers for RTL
structures, as well as an extensive line of more then 25
protocol monitors for standard interfaces and protocols.
-- Interoperable assertions in simulation - the ability to use
assertions in any of the standard formats including
CheckerWare, PSL, System Verilog and OVL.
-- Coverage information - actionable implementation-based unified
structural coverage to measure progress towards complete
verification.
-- Formal verification - exhaustive static and dynamic formal
verification to unleash enormous computational power for
finding bugs missed by simulation.
Archer Verification includes structural coverage information that
complements functional coverage to provide a complete RTL coverage
model. Structural coverage measures verification activity within RTL
structures such as arbiters and FIFO buffers based on the corner-cases
specific to each structure. For example, structural coverage of a FIFO
buffer measures whether the FIFO was empty, full or has reached a
high-water mark. The structural coverage metrics are integrated with
the CheckerWare library and help users identify areas of their designs
that require further verification to find corner-case bugs.
Archer Verification also provides a complete exhaustive formal
verification capability that includes both static and dynamic formal
verification. The Archer Verification methodologies apply formal
analysis on verification issues where simulation alone is
insufficient. The well-defined methods allow all design and
verification engineers to benefit from the power of formal analysis,
leading to a predictable improvement in verification time and effort.
Archer Verification Products Address Specific Verification
Challenges
Archer-CDV supports a coverage-driven verification (CDV) flow in
which metrics are used to gauge the effectiveness of each step in the
test plan and to determine which areas of the design need more
verification effort. Archer-CDV provides automatic static checks and
user-specified assertions running in simulation. Archer-CDV includes
the CheckerWare library of verification IP that combines assertion
checking with functional coverage collection. CheckerWare library
elements also integrate management and debugging capabilities,
allowing users to assess both assertion quality and verification
completeness.
Archer-SF supports a full static formal (SF) verification flow
that can find bugs in designs before a simulation environment is
available. Archer-SF provides support for automatic design checks and
user-specified assertions. These design checks and assertions can be
analyzed using formal static verification engines that produce
counterexamples showing ways to violate assertions and proofs if no
such violations are possible. Integrated formal verification metrics
provide feedback on the quality of the assertions as well as the
amount of exhaustive formal analysis performed.
Archer-ABV supports a chip- or system-level verification flow by
providing a complete solution with the full range of assertion-based
verification (ABV) tools and methodologies and by combining exhaustive
formal verification with simulation to find bugs missed by all other
methods. Archer-ABV includes the capabilities of Archer-SF and
Archer-CDV as well as 0-In's unique dynamic formal verification
engines to leverage interesting and hard-to-reach corner-cases
exercised in chip- or system-level simulations. By applying formal
analysis at the right critical moments, RTL bugs can be found that
would otherwise reach silicon. Unified coverage metrics from
Archer-ABV provide feedback on the quality of the assertions, the
degree of design exercised in simulation and the amount of additional
coverage provided by the dynamic formal analysis.
Pricing and Availability
The 0-In Archer Verification System is available immediately.
North America list prices are: Archer-CDV $50,000; Archer-SF $60,000;
and Archer-ABV $120,000.
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and
supports functional verification products that help verify
multi-million gate application-specific integrated circuit (ASIC) and
system-on-chip (SoC) designs. The company delivers a comprehensive
assertion-based verification (ABV) solution built on industry
standards that provides value throughout the design and verification
cycle -- from the block level to the chip and system levels. Twelve of
the 15 largest electronics companies have adopted 0-In tools and
methodologies in their integrated circuit (IC) design verification
flows. 0-In was founded in 1996 and is based in San Jose, Calif. For
more information, see http://www.0-in.com.
0-In(R) and CheckerWare(R) are registered trademarks of 0-In
Design Automation, Inc. All other trademarks are the property of their
respective holders.
Contact:
0-In Design Automation
Steve White, 408-487-3649
swhite@0-in.com
or
Cayenne Communication
(for 0-In Design Automation)
Linda Marchant, 919-683-9545
linda.marchant@cayennecom.com
|
|
|
